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w WM8523 24-bit 192khz stereo dac with 2vrms ground referenced line output wolfson microelectronics plc production data, august 2013, rev 4.2 copyright ? 2013 wolfson microelectronics plc description the WM8523 is a stereo dac with integral charge pump and software control interface. this provides 2vrms line driver outputs using a single 3.3v power supply rail. the device features ground-referenced outputs and the use of a dc servo to eliminate t he need for line driving coupling capacitors and effectively eliminate power on pops and clicks. the device is controlled and configured either via the i2c/spi compliant serial control interface or a hardware control interface. the device supports all common audio sampling rates between 8khz and 192khz using all common mclk fs rates. master and slave modes are available and de- emphasis is also supported. the WM8523 has a 3.3v tolerant digital interface, allowing logic up to 3.3v to be connected. the device is available in a 20-lead tssop package. features ? high performance stereo dac with ground referenced line driver ? audio performance ? 106db snr (?a-weighted?) ? -89db thd @ -1dbfs ? digital volume control ranging from -100db to +12db ? 120db mute attenuation ? all common sample rates from 8khz to 192khz supported ? i 2 c/spi compatible and hardware control modes ? data formats: lj, rj, i 2 s, dsp ? de-emphasis supported ? maximum 1mv dc offset on line outputs ? pop/click suppressed power up/down sequencer ? avdd and linevdd +3.3v 10% allowing single supply ? 20-lead tssop package ? operating temperature range: -40c to 85c applications ? consumer digital audio applic ations requiring 2vrms output ? set top box ? digital tv ? dvd players ? games consoles ? a/v receivers
WM8523 production data w pd, rev 4.2, august 2013 2 block diagram lrclk dacdat linevoutl linevoutr digital audio interface digital filters control interface left dac right dac WM8523 bclk mclk cs/mute sclk/aifmode1 sda/aifmode0 cpca cpcb sdout/deemph charge pump cpvoutn agnd vmid linevdd linegnd avdd cifmode zflag
production data WM8523 w pd, rev 4.2, august 2013 3 table of contents descript ion ................................................................................................................... . 1 ? featur es ...................................................................................................................... ... 1 ? applications .................................................................................................................. 1 ? block diag ram ............................................................................................................. 2 ? table of co ntents ...................................................................................................... 3 ? pin config uration ....................................................................................................... 4 ? ordering info rmation ............................................................................................... 4 ? pin descri ption ............................................................................................................. 5 ? absolute maximu m ratings ..................................................................................... 6 ? recommended operatin g condit ions .................................................................. 6 ? electrical charact eristics .................................................................................. 7 ? terminology ................................................................................................................... ......... 7 ? power consumption measurements .............................................................................. 8 ? signal timing re quiremen ts ................................................................................... 9 ? system clock timing ........................................................................................................... .. 9 ? audio interface timing ? master mode .......................................................................... 9 ? audio interface timi ng ? slave mode ........................................................................... 10 ? control interface timing ? i 2 c mode ............................................................................ 11 ? control interface timi ng ? spi mode ........................................................................... 12 ? power on reset circuit .................................................................................................... 13 ? device des cription ................................................................................................... 15 ? introduction .................................................................................................................. ....... 15 ? software control interface......................................................................................... 15 ? digital audio interface ..................................................................................................... 1 9 ? digital audio interface control ................................................................................... 22 ? digital audio data sampling rates ............................................................................... 24 ? dac features .................................................................................................................. ....... 25 ? hardware control interface ........................................................................................ 30 ? power do mains ................................................................................................................. .... 32 ? register map ............................................................................................................... 33 ? register bits by address ................................................................................................. 34 ? digital filter charact eristics ........................................................................... 38 ? dac filter r esponses ........................................................................................................ 3 9 ? digital de-emphasis characteristics .......................................................................... 40 ? applications in formation ..................................................................................... 41 ? recommended external components ......................................................................... 41 ? recommended pcb layout ................................................................................................ 42 ? recommended analogue low pass filter .................................................................. 43 ? relevant application notes ............................................................................................ 43 ? package dime nsions ................................................................................................. 44 ? important no tice ...................................................................................................... 45 ? address ....................................................................................................................... ............ 45 ? revision hi story ........................................................................................................ 46 ?
WM8523 production data w pd, rev 4.2, august 2013 4 pin configuration 11 12 13 14 15 16 17 18 19 mclk sdout/deemph sda/aifmode0 sclk/aifmode1 cs/mute cifmode 20 10 9 8 7 6 5 4 3 2 1 agnd vmid avdd linevoutr bclk lrclk dacdat zflag linevdd linegnd cpca cpcb cpvoutn linevoutl 20-lead tssop ordering information order code temperature range package moisture sensitivity level peak soldering temperature WM8523gedt ? 40c to +85c 20-lead tssop (pb-free) msl1 260 o c WM8523gedt/r ? 40c to +85c 20-lead tssop (pb-free, tape and reel) msl1 260 o c note: reel quantity = 2000
production data WM8523 w pd, rev 4.2, august 2013 5 pin description pin no name type description 1 linevoutl analogue out left line output 2 cpvoutn analogue out charge pump negative rail decoupling pin 3 cpcb analogue out charge pump fly back capacitor pin 4 linegnd supply charge pump ground 5 cpca analogue out charge pump fly back capacitor pin 6 linevdd supply charge pump supply 7 zflag digital out zero flag output 8 dacdat digital in digital audio interface data input 9 lrclk digital i/o digital audio interface left/right clock 10 bclk digital i/o digital audio interface bit clock 11 mclk digital in master clock i 2 c software mode spi software mode hardware mode 12 sdout/ deemph digital i/o i 2 c address select bit[1] serial control interface data output pin 0 ? no de-emphasis 1 ? de-emphasis 13 sda/ aifmode0 digital i/o internal pull-down serial control interface data input pin serial control interface data input pin aifmode[1:0] 00 ? lj 24 bits 01 ? i2s 24 bits 10 ? rj 16 bits 11 ? rj 24 bits 14 sclk/ aifmode1 digital i/o internal pull-down serial control interface clock input pin serial control interface clock input pin 15 cs / mute digital in i 2 c address select bit[0] serial control interface chip select 0 ? mute enabled 1 ? mute disabled 16 cifmode digital in tri-level 0 ? i 2 c compatible mode select 1 ? spi compatible mode select z ? hardware mode 17 agnd supply analogue ground 18 vmid analogue out analogue midrail decoupling pin 19 avdd supply analogue supply 20 linevoutr analogue out right line output note: tri-level pins which require the ?z? stat e to be selected should be left floating (open)
WM8523 production data w pd, rev 4.2, august 2013 6 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guar anteed performance specifications are given under electrical characteristics at the te st conditions specified. esd sensitive device. this device is manufactur ed on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-st d-020 for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 ? c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specif ied in ordering information. condition min max avdd, linevdd -0.3v +4.5v voltage range digital inputs linegnd -0.3v linevdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v temperature range, t a -40c +125c storage temperature after soldering -65c +150c notes 1. analogue grounds must always be within 0.3v of each other. 2. linevdd and avdd must always be within 0.3v of each other. recommended operating conditions parameter symbol test conditions min typ max unit analogue supply range avdd, linevdd 2.97 3.3 3.63 v ground agnd, linegnd 0 v
production data WM8523 w pd, rev 4.2, august 2013 7 electrical characteristics test conditions linevdd=avdd=3.3v, linegnd=agnd=0v, t a =+25 c, slave mode, fs=48khz, mclk=256f s, 24-bit data, unless otherwise stated. parameter symbol test conditions min typ max unit analogue output levels output level 0dbfs 1.89 2.1 2.31 vrms load impedance 1 k ? load capacitance no external rc filter 300 pf with filter shown in figure 39. 1 f dac performance signal to noise ratio snr r l = 10k ? a-weighted 100 106 db r l = 10k ? un-weighted 104 db dynamic range dnr r l = 10k ? a-weighted 104 db total harmonic distortion thd r l = 10k ? -1dbfs -89 db r l = 10k ? 0dbfs -86 db avdd + linevdd power supply rejection ratio psrr 100hz 54 db 1khz 54 db 20khz 50 db channel separation 1khz 100 db 20hz to 20khz 95 db system absolute phase 0 degrees channel level matching 0.1 db mute attenuation -120 db dc offset at linevoutl and linevoutr -1 0 1 mv digital logic levels input high level v ih 0.7 ? linevdd v input low level v il 0.3 ? linevdd v output high level v oh i ol = 1ma 0.9 ? linevdd v output low level v ol i oh = -1ma 0.1 ? linevdd v input capacitance 10 pf input leakage -0.9 0.9 ? a terminology 1. signal-to-noise ratio (db) ? snr is a measure of the difference in level between the maximum theoretical full scale output s ignal and the output with no input signal applied. 2. total harmonic distortion (db) ? thd is the level of the rms value of the sum of harmonic distortion products relative to th e amplitude of the measured output signal. 3. all performance measurements carried out with 20khz low pass filter, and where noted an a-weighted filter. failure to use s uch a filter will result in higher thd and lower snr readings than are f ound in the electrical characteri stics. the low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 4. mute attenuation ? this is a measure of the difference in level between the full scale output signal and the output with mut e applied.
WM8523 production data w pd, rev 4.2, august 2013 8 power consumption measurements test conditions linevdd=avdd=3.3v, linegnd=agnd=0v, t a =+25c, slave mode, quiescent (no signal) test conditions iavdd (ma) ilinevdd (ma) total (ma) off no clocks applied sys_ena[1:0]=00 0.8 1.1 1.9 fs=48khz, mclk=256fs standby sys_ena[1:0]=01 0.2 2.2 2.4 playback sys_ena[1:0]=11 4.8 6.0 10.8 fs=96khz, mclk=256fs standby sys_ena[1:0]=01 0.2 2.9 3.1 playback sys_ena[1:0]=11 5.5 8.5 14.0 fs=192khz, mclk=128fs standby sys_ena[1:0]=01 0.2 2.9 3.1 playback sys_ena[1:0]=11 5.5 8.5 14.0
production data WM8523 w pd, rev 4.2, august 2013 9 signal timing requirements system clock timing figure 1 system clock timing requirements test conditions linevdd=avdd=2.97~3.63v, linegnd=agnd=0v, t a =+25c parameter symbol min typ max unit master clock timing information mclk cycle time t mclky 27 500 ns mclk high time t mclkh 11 ns mclk low time t mclkl 11 ns mclk duty cycle (t mclkh /t mclkl) 40:60 60:40 % audio interface timing ? master mode figure 2 master mode digital audio data timing test conditions linevdd=avdd=2.97~3.63, linegnd=agnd=0v, t a =+25c, master mode parameter symbol min typ max unit audio data input timing information lrclk propagation delay from bclk falling edge t dl 4 16 ns dacdat setup time to bclk rising edge t dst 22 ns dacdat hold time to bclk falling edge t dht 25 ns table 1 master mode audio interface timing
WM8523 production data w pd, rev 4.2, august 2013 10 audio interface timing ? slave mode figure 3 digital audio data timing ? slave mode test conditions linevdd=avdd=2.97~3.63v, linegnd=agnd=0v, t a =+25 c, slave mode parameter symbol min typ max unit audio data input timing information bclk cycle time t bcy 27 ns bclk pulse width high t bch 11 ns bclk pulse width low t bcl 11 ns lrclk set-up time to bclk rising edge t lrsu 7 ns lrclk hold time from bclk rising edge t lrh 5 ns dacdat hold time from lrclk rising edge t dh 5 ns dacdat set-up time to bclk rising edge t ds 7 ns table 2 slave mode audio interface timing note: bclk period should always be greater than or equal to mclk period.
production data WM8523 w pd, rev 4.2, august 2013 11 control interface timing ? i 2 c mode i 2 c mode is selected by driving the cifmode pin low. figure 4 control interface timing ? i 2 c control mode test conditions linevdd=avdd=2.97~3.63v, linegnd=agnd=0v, t a =+25c parameter symbol min typ max unit program register input information sclk frequency 400 khz sclk low pulse-width t 1 100 ns sclk high pulse-width t 2 100 ns hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sda, sclk rise time t 6 300 ns sda, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed 2 8 ns table 3 control interface timing ? i 2 c control mode
WM8523 production data w pd, rev 4.2, august 2013 12 control interface timing ? spi mode spi mode is selected by connecting the cifmode pin high. figure 5 control interface timing ? spi control mode (read cycle) test conditions linevdd=avdd=2.97~3.63v, linegnd=agnd=0v, t a =+25c parameter symbol min typ max unit program register input information sclk rising edge to csb falling edge t csu 40 ns sclk falling edge to csb rising edge t cho 40 ns sclk pulse cycle time t scy 160 ns sclk pulse width low t scl 64 ns sclk pulse width high t sch 64 ns sda to sclk set-up time t dsu 20 ns sda to sclk hold time t dho 40 ns sdout propagation delay from sclk falling edge t dl 5 ns pulse width of spikes that will be suppressed t ps 2 8 ns table 4 control interface timing ?spi control mode
production data WM8523 w pd, rev 4.2, august 2013 13 power on reset circuit figure 6 internal power on reset circuit schematic the WM8523 includes an internal power-on-reset circuit, as shown in figure 6, which is used to reset the dac digital logic into a default state after power up. the por circuit is powered by avdd and has as its inputs vmid and linevdd. it asserts por low if vm id or linevdd are below a minimum threshold. figure 7 typical power timing requirements figure 7 shows a typical power-up sequence where linevdd comes up with avdd. when avdd goes above the minimum threshold, v pora , there is enough voltage for the circuit to guarantee por is asserted low and the chip is held in reset. in this condition, a ll writes to the control interface are ignored. after vmid rises to v pord_hi and avdd rises to v pora_hi, por is released high and all registers are in their default state and writes to the control interface may take place. on power down, porb is asserted low whenever li nevdd or avdd drop below the minimum threshold v pora_low .
WM8523 production data w pd, rev 4.2, august 2013 14 test conditions linevdd = avdd = 3.3v agnd = linegnd = 0v, t a = +25 o c parameter symbol test conditions min typ max unit power supply input timing information vdd level to por defined (linevdd/avdd rising) v pora measured from linegnd 158 mv vdd level to por rising edge (vmid rising) v pord_hi measured from linegnd 0.63 0.8 1 v vdd level to por rising edge (linevdd/avdd rising) v pora_hi measured from linegnd 1.44 1.8 2.18 v vdd level to por falling edge (linevdd/avdd falling) v pora_lo measured from linegnd 0.96 1.46 1.97 v table 5 power on reset note: all values are simulated results
production data WM8523 w pd, rev 4.2, august 2013 15 device description introduction the WM8523 provides high fidelity, 2v rms ground referenced stereo line out put from a single supply line with minimal external components. the integrated dc se rvo eliminates the requirement for external mute circuitry by minimising dc transients at the output during power up/down. the device is well-suited to both stereo and multi-channel systems. the device supports all common audio sampling ra tes between 8khz and 192khz using common mclk fs rates. master and slave modes are available. the WM8523 supports both hardware and software control modes. in hardware control mode, the digital audio interface format is switchable between 16 to 24bits lj, rj and i 2 s. mute and de-emphasis contro l pins are also available. in software control modes the digital audio interface is highly programmable, with four control interface addresses to allow multiple WM8523 devices to be configured independently. software control interface software control mode is selected by logic 1 or 0 on t he cifmode pin. the logic level is referenced to the linevdd power domain. when software mode is se lected, the associated multi-function control pins are defined as described in table 6. pin name pin number description sdout 12 i 2 c mode - device address[1] spi mode - serial data output sda 13 serial data input sclk 14 serial data clock cs 15 i 2 c mode - device address[0] spi mode - chip select cifmode 16 control interface mode 0 = i 2 c mode 1 = spi mode z = hardware mode table 6 software control pin configuration in software control mode, the WM8523 is controlled by writing to its control registers. readback is available for all registers, including device id and pow er management status bits. the control interface can operate as an i 2 c or spi control interface: register read- back is provided on the bi-directional pin sda in i 2 c mode, and on the sdout pin in spi mode. the WM8523 software control interface is supplied by the linevdd power domain. the available software control interf ace modes are summarised as follows: ? i 2 c mode uses pins sclk and sda. ? spi mode uses pins cs , sclk and sda and sdout. i 2 c mode is selected by setting the cifmode pin to logi c 0. when cifmode is set to logic 1, spi mode is selected.
WM8523 production data w pd, rev 4.2, august 2013 16 i 2 c control mode in i 2 c mode, the WM8523 is a slave device on the control in terface; sclk is a clock input, while sda is a bi-directional data pin. to allow arbitration of mult iple slaves (and/or multip le masters) on the same interface, the WM8523 transmits logic 1 by tri-stating t he sda pin, rather than pulling it high. an external pull-up resistor is required to pull the sda line high so that the logic 1 can be recognised by the master. in order to allow many devices to share a single i 2 c control bus, every devic e on the bus has a unique 7- bit device address (this is not the same as the 8-bi t address of each register in the WM8523). the device address is determined by the logic level on the sdout and cs pins as shown in table 7. the lsb of the device address is the r/w bit; this bit is set to logic 1 for ?read? and logic 0 for ?write?. sdout addr1 cs addr0 device address 0 0 0011 0100 (34h) 0 1 0011 0110 (36h) 1 0 0011 1100 (3ch) 1 1 0011 1110 (3eh) table 7 control interface device address selection the WM8523 operates as an i 2 c slave device only. the controller indi cates the start of data transfer with a high to low transition on sda while sclk remains high. this indicates that a device address, register address and data will follow. all devices on the i 2 c bus respond to the start condition and shift in the next eight bits on sda (7-bit device address + read/writ e bit, msb first). if the device address received matches the device address of the WM8523, then t he WM8523 responds by pulling sda low on the next clock pulse (ack). if the device addr ess is not recognised or the r/w bit is ?1? when operating in write only mode, the WM8523 returns to the idle condi tion and waits for a new start condition and valid address. if the device address matches the device address of the WM8523, the data transfer continues as described below. the controller indicates the end of data transfer with a low to high transition on sda while sclk remains high. after receiving a complete address and data sequence the WM8523 returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sda changes wh ile sclk is high), the device returns to the idle condition. the WM8523 supports the following read and write operations: ? single write ? single read
production data WM8523 w pd, rev 4.2, august 2013 17 the sequence of signals associated with a single regi ster write operation is illustrated in figure 8. figure 8 control interface i 2 c register write the sequence of signals associated with a single regi ster read operation is illustrated in figure 9. figure 9 control interface i 2 c register read figure 10 single register write to specified address figure 11 single register read from specified address
WM8523 production data w pd, rev 4.2, august 2013 18 spi control mode the WM8523 can also be controlled by writing to register s through a spi control interface. a control word consists of 24 bits. the firs t bit is the read/write bit (r/w ), which is followed by 7 address bits (a6 to a0) that determine which control register is accessed. the remaining 16 bits (b15 to b0) are data bits, corresponding to the 16 bits in each control register. volume update registers r06h and r07h are unavailable in spi control mode. to use volume update in software control mode, i 2 c mode must be used. in spi mode, every rising edge of sclk clocks in one data bit from the sda pin. a rising edge on cs latches in a complete control word consisting of the last 24 bits. the spi mode write operation protocol is illustrated in figure 12. figure 12 spi control interface ? write operation in write operations (r/w =0), all sda bits are driv en by the controlling device. in read operations (r/w =1), the sda pin is ignored following receip t of the valid register address. the data bits are output by the WM8523 on the sdout pin. the spi mode read operation protocol is illustrated in figure 13. figure 13 spi control interface ? read operation register reset any write to register r0 (00h) will reset the WM8523. a ll register bits are reset to their default values. device id and revision reading from register r0 (00h) returns the device id. reading from register r1 returns the device revision number. register address bit label default description r0 device_id 00h 15:0 device_id [15:0] 10000101 00100011 device id a read of this register will return the device id, 0x8523. r1 revision 01h 2:0 chip_rev [2:0] n/a device revision a read of this register will return the device revision number. this number is sequentially incremented if the device design is updated. table 8 device id and revision number
production data WM8523 w pd, rev 4.2, august 2013 19 digital audio interface the digital audio interface is us ed for inputting audio data to the wm 8523. the digital audio interface uses three pins: ? dacdat: dac data input ? lrclk: left/right data alignment clock ? bclk: bit clock, for synchronisation in software control mode, all interface data formats and modes of operation can be selected. in hardware control mode, only a subset of formats and modes ar e supported ? see the hardware interface control section on page 30 for details. master and slave mode operation the WM8523 digital audio interface can operate as a ma ster or as a slave as shown in figure 14 and figure 15. figure 14 slave mode figure 15 master mode interface formats the WM8523 supports five different audio data formats: ? left justified ? right justified ? i 2 s ? dsp mode a ? dsp mode b pcm operation is supported using the dsp mode. all seven of these modes are msb first. they are described in audio data formats on page 20. refer to the ?electrical characteristics? section for timing information. refer to table 10 for inte rface control format register settings.
WM8523 production data w pd, rev 4.2, august 2013 20 audio data formats in right justified mode, the lsb is available on the last rising edge of bclk before a lrclk transition. all other bits are transmitted before (msb first). depending on word length, bclk frequency and sample rate, there may be unused bclk cycles after each lrclk transition. figure 16 right justified audio interface (assuming n-bit word length) in left justified mode, the msb is available on the fi rst rising edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each lrclk transition. figure 17 left justified audio interface (assuming n-bit word length) in i 2 s mode, the msb is available on the second rising edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next. figure 18 i 2 s justified audio interface (assuming n-bit word length)
production data WM8523 w pd, rev 4.2, august 2013 21 in dsp mode, the left channel msb is available on either the 1 st (mode b) or 2 nd (mode a) rising edge of bclk (selectable by aif_lrclk_inv) following a ri sing edge of lrclk. right channel data immediately follows left channel data. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. in device master mode, the lrclk output will rese mble the frame pulse shown in figure 19 and figure 20. in device slave mode, figure 21 and figure 22, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pul se occurs greater than one bclk period before the rising edge of the next frame pulse. figure 19 dsp mode audio interface (mode a, aif_lrclk_inv=0, master) figure 20 dsp mode audio interface (mode b, aif_lrclk_inv=1, master) figure 21 dsp mode audio interface (mode a, aif_lrclk_inv=0, slave)
WM8523 production data w pd, rev 4.2, august 2013 22 figure 22 dsp mode audio interface (mode b, aif_lrclk_inv=1, slave) digital audio interface control the control of the audio interface in software mode is achieved by register write. dynamically changing the audio data format may cause err oneous operation and is not recommended. digital audio data is transferred to the WM8523 via t he digital audio interface. the dac operates in master or slave mode. the dac audio interface requires left/right frame cl ock (lrclk) and bit clock (bclk). these can be supplied externally (slave mode) or they can be generat ed internally (master mode). selection of master and slave mode is achieved by setting aif_mstr bit in register 3. the frequency of lrclk in master mode is dependent upon the dac master clock frequency and the aif_sr[2:0] bits. the frequency of bclk in master mode can be selected by aif_bclkdiv[2:0]. in slave mode, the mclk to lrclk ratio can be auto-det ected or set manually using the aif_sr[2:0] bits. register address bit label default description r3 aif_ctrl1 03h 7 aif_mstr 0 master/slave select 0 = slave 1 = master r4 aif_ctrl2 04h 2:0 aif_sr[2:0 000 mclk:lrclk ratio 000 = auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs 5:3 aif_bclkd iv[2:0] 000 bclk divider control (master mode) 000 = mclk/4 001 = mclk/8 010 = 32fs 011 = 64fs 100 = 128fs 101 - 111 reserved table 9 dac clocking mode control
production data WM8523 w pd, rev 4.2, august 2013 23 interface timing is such that the input data and left/r ight clock are sampled on the rising edge of bclk. by setting the appropriate bclk and lrclk polarity bits, the WM8523 dac can sample data on the opposite clock edges. the control of audio interface formats and cl ock polarities is summarised in table 10. register address bit label default description r3 aif_ctrl1 03h 1:0 aif_fmt 10 audio data interface format 00 = right justified 01 = left justified 10 = i2s format 11 = dsp mode 2 reserved 0 reserved 4:3 aif_wl 10 audio data word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits 5 aif_bclk_ inv 0 bclk inversion control slave mode: 0 = use rising edge 1 = use falling edge master mode: 0 = bclk normal 1 = bclk inverted 6 aif_lrclk _inv 0 lrclk inversion control 0 = normal polarity 1 = inverted polarity when aif_fmt[2:0]=011 (dsp mode): 0 = mode a (2nd clock) 1 = mode b (1st clock) table 10 audio interface control
WM8523 production data w pd, rev 4.2, august 2013 24 digital audio data sampling rates the external master clock is appli ed directly to the mclk input pin. in a system where there are a number of possible sources for the reference clock, it is recommended that the clock source with the lowest jitter be used for the master clock to optimise the performance of the WM8523. in slave mode the WM8523 has a detec tion circuit that automatically determines the relationship between the master clock frequency (mclk) and the sampling rate (lrclk), to within 32 system clock periods. the mclk must be synchronised with the lrclk, alt hough the device is tolerant of phase variations or jitter on the mclk. if the device is configured in slav e mode using auto-detect or in hardware mode, and during sample rate change the ratio between mclk and lrclk varies more than once within 1026 lrclk periods, then it is recommended that the device be taken into the standby state or the off state before the sample rate change and held in standby until the sample rate change is complete. this will ensure correct operation of the detection circuit on the return to the enabled state. for details on the standby state, please refer to the software control interface (software mode, page 15) and power up and down control in hardware mode section of the datasheet (hardware mode, on page 31). the dac supports mclk to lrclk ratios of 128fs to 1152fs and sampling rates of 8khz to 192khz, provided the internal signal processing of the da c is programmed to operate at the correct rate. table 11 shows typical master clock frequencies and sampling rates supported by the WM8523 dac. sampling rate lrclk master clock frequency (mhz) 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 8khz unavailable unavailable 2.048 3.072 4.096 6.144 9.216 32khz unavailable unavailable 8.192 12.288 16.384 24.576 36.864 44.1khz unavailable unavailable 11.2896 16.9344 22.5792 33.8688 unavailable 48khz unavailable unavailable 12.288 18.432 24.576 36.864 unavailable 88.2khz 11.2896 16.9344 22.5792 33.8688 unavailabl e unavailable unavailable 96khz 12.288 18.432 24.576 36.864 unavailabl e unavailable unavailable 176.4khz 22.5792 33.8688 unavailable unavailable u navailable unavailable unavailable 192khz 24.576 36.864 unavailable unavailable u navailable unavail able unavailable table 11 mclk frequencies and audio sample rates
production data WM8523 w pd, rev 4.2, august 2013 25 dac features system enable the WM8523 includes a number of enable and disable me chanisms to allow the device to be powered on and off in a pop-free manner. the sys_ena[1:0] control bits enable the dac and analogue paths. register address bit label default description r2 psctrl1 02h 1:0 sys_ ena[1:0] 00 system power control 00 = off 01 = power down 10 = power up and mute 11 = power up and unmute table 12 system enable control note: mclk must be present at all times when using t he sys_ena[1:0] bits. if mclk is stopped at any point the device will power down to the ?off? state, but all register settings will remain. restarting mclk will start the device internal power sequence and the dev ice will return to the power state set by the sys_ena[1:0] bits. the power up and power down sequences are summarised in figure 23. there is no requirement to manually cycle the device through the sequence via register writes, as the device will always automatically step through each stage in the sequence. power up when sys_ena[1:0]=00, the internal clocks ar e stopped and all analogue and digital blocks are disabled for maximum power saving. the device starts up in this state in software mode. setting sys_ena[1:0]=01 enables the internal charge pump and required control circuitry, but the signal path remains powered down. when sys_ena[1:0]=10 a ll blocks are powered up sequentially and full system configuration is achieved. once th is is complete, the device is ready to pass audio but is muted. setting sys_ena[1:0]=11 releases the mute and audio playback begins. power down when sys_ena[1:0]=11 the device is powered up and passing audio. changing sys_ena[1:0]=10 applies a digital softmute to the output. setting sys_ena[1:0]=01 sequentially powers down all circuit blocks but leaves the charge pump and required control circuitry enabled. this can be considered the low-power standby state. finally, setting sys_ena[1: 0]=00 will disable all circuit blocks including the charge pump, and full system initialisation will be required to restart the device.
WM8523 production data w pd, rev 4.2, august 2013 26 sys_ena = 00 sys_ena = 01 sys_ena = 10 sys_ena = 11 enable charge pump enable digits enable amplifier enable dac mute output unmute output disable charge pump disable digits disable amplifier disable dac mute output figure 23 sys_ena[1:0] power up and down sequences digital volume control the WM8523 dac includes digital volume control, allowing the digital gain to be adjusted between ? 100db and +12db in 0.25db steps. volume update bits allow the user to write both left and right channel volume changes before the volume is updated. digital volume control is only available in i 2 c mode. register address bit label default description r6 dac_gainl 06h 8:0 dacl _vol[8:0] 110001000 dac digital volume 0 0000 0000 = ? 100db 0 0000 0001 = ? 99.75db 0 0000 0010 = ? 99.5db ?0.25db steps 1 1001 0000 = 0db ?0.25db steps 1 1011 1110 = +11.75db 1 11xx xxxx = +12db r7 dac_gainr 07h 8:0 dacr _vol[8:0] r6 dac_gainl 06h 9 dacl_vu 0 dac digital volume update 0 = latch dac volume setting into register map but do not update volume 1 = latch dac volume setting into register map and update left and right channels simultaneously r7 dac_gainr 07h 9 dacr_vu 0 table 13 dac digital volume control
production data WM8523 w pd, rev 4.2, august 2013 27 volume change modes volume can be adjusted by step change (either using ze ro cross or not) or by soft ramp. the volume change mode is controlled by the dac_vol_dow n_ramp and dac_vol_up_ramp bits in r5: register address bit label default description r5 dac_ctrl3 05h 0 dac_vol _down_ ramp 1 dac digital volume decrease control 0 = apply volume decreases instantly (step) 1 = ramp volume decreases 1 dac_vol _up_ ramp 0 dac digital volume increase control 0 = apply volume increases instantly (step) 1 = ramp volume increases table 14 volume ramp control figure 24 illustrates the effect of the volume ramp: dac_vol_down_ramp=1 dac_vol_up_ramp=1 dac_vol_down_ramp=0 dac_vol_up_ramp=0 figure 24 volume ramp functionality
WM8523 production data w pd, rev 4.2, august 2013 28 ramp volume changes if ramp volume changes are selected, the ramp rate is dependent upon the sampling rate. the ramp rates for common audio sample rates are shown in table 15. sample rate for dac (khz) gain ramp rate (ms/db) 8 1 32 0.25 44.1 0.18 48 0.17 88.2 0.1 96 0.08 176.4 0.05 192 0.04 table 15 volume ramp rate for example, when using a sample rate of 48khz, the time taken for a volume change from an initial setting of 0db to -20db is calculated as follows: volume change (db) x volume ramp rate (ms/db) = 20 x 0.17 = 3.4ms zero cross is not used when ramping. the volume level in the dac is set by the user in 0.25db increments, but during the volume ramp increments of 0.125db are actually used. this step size is inaudible and means there is no requirement to wait unt il a zero crossing occurs. another benefit of not using zero cross when ramping is that predict able ramp times are produced ? there is no signal dependency on the ramp time. step volume changes and zero cross the step volume control includes optional zero cro ss functionality. when zero cross is enabled, by setting dac_zcen=1, volume changes are not applied until the signal crosses zero so no discontinuity is seen in the output signal. zero cross helps to pr event pop and click noise when changing volume settings and is therefore recommended if using step volume changes. the zero cross function includes a timeout which forc es volume changes if a zero cross event does not occur. the timeout period is 14400 samples, equivalent to 300ms at 48khz sample rate. register address bit label default description r5 dac_ctrl3 05h 4 dac_ zcen 0 zero cross enable 0 = do not use zero cross 1 = use zero cross table 16 zero cross control table 17 gives a summary of the volume mode settings and their effect. dac_vol_ up_ramp dac_vol_ down_ramp dac_zcen volume change up volume change down 0 0 0 step, no zero cross step, no zero cross 0 1 0 step, no zero cross ramp 1 0 0 ramp step, no zero cross 1 1 0 ramp ramp 0 0 1 step, use zero cross step, use zero cross 0 1 1 step, use zero cross ramp 1 0 1 ramp step, use zero cross 1 1 1 ramp ramp table 17 volume change summary
production data WM8523 w pd, rev 4.2, august 2013 29 mute a digital mute can be applied to left and right channels independently. register address bit label default description r5 dac_ctrl3 05h 2 dacl_ mute 0 left dac mute 0 = normal operation 1 = mute r5 dac_ctrl3 05h 3 dacr_ mute 0 right dac mute 0 = normal operation 1 = mute table 18 dac mute control the dac mute function in software mode is contro lled by the register settings dac_vol_up_ramp, dac_vol_down_ramp and dac_zcen as described in table 17 . digital monomix control the dac can be set to output a range of m ono and stereo options using dac_op_mux[1:0]. register address bit label default description r4 aif_ctrl2 04h 7:6 dac_op_ mux[1:0] 00 dac digital monomix 00 = stereo (normal operation) 01 = mono (left data to dacr) 10 = mono (right data to dacl) 11 = digital monomix, (l+r)/2 table 19 digital monomix control de-emphasis a digital de-emphasis filter may be applied to the dac output when the sampling frequency is 44.1khz. operation at 48khz and 32khz is also possible, but with an increase in the error from the ideal response. details of the de-emphasis filter characteristic fo r 32khz, 44.1khz and 48khz c an be seen in figure 31 to figure 36. register address bit label default description r3 aif_ctrl1 03h 6 dac _deemp 0 dac de-emphasis 0 = no de-emphasis 1 = apply de-emphasis table 20 de-emphasis control zero detect the infinite zero detect allows the user to select the number of zero samples received before the zflag pin is asserted high, as described in table 21. register address bit label default description r8 zero_detect 08h 0 zd_ count 0 zero detect count control 0 = 1024 1 = 2048 table 21 zero detect control
WM8523 production data w pd, rev 4.2, august 2013 30 hardware control interface the WM8523 can be controlled in hardware mode or in software modes. in hardware mode, the device is configured according to logic leve ls applied to hardware pins. hardware control mode is selected by leavi ng cifmode pin open-circui t (high-impedance). when hardware mode is selected, the associated multi-func tion control pins are defi ned as described in table 22. pin name pin name pin number description tssop qfn zflag 7 24 zero flag output 0 = normal operation 1 = infinite zero detect is triggered or mute is applied deemph 12 5 de-emphasis filter select 0 = filter disabled 1 = filter enabled aifmode0 13 6 aifmode1 0 0 1 1 aifmode0 0 1 0 1 format 24-bit left justified 24-bit i 2 s 16-bit right justified 24-bit right justified aifmode1 14 7 mute 15 8 mute control 0 = mute 1 = normal operation cifmode 16 9 control interface mode 0 = i 2 c mode 1 = spi mode z = hardware mode table 22 hardware control pin configuration de-emphasis a digital de-emphasis filter may be applied to the dac output when the sampling frequency is 44.1khz. operation at 48khz and 32khz is also possible, but with an increase in the error from the ideal response. details of the de-emphasis filter characteristic fo r 32khz, 44.1khz and 48khz c an be seen in figure 31 to figure 36. mute in hardware mode, the mute pin controls the dac mute to both left and right channels. when the mute is asserted a softmute is applied to ramp the signal down, with the ramp rate related to the sample rate as defined in table 15 on page 28. once mute is achiev ed, the zflag is asserted. when the mute is de- asserted the signal returns to full scale in one step and the zflag is de-asserted. zero detect the zero detect function in hardware mode will assert the zflag pin high when 1024 zero count samples are input to the digital audio interface. additiona lly, the zflag is asserted when the device is muted using the mute pin and also until the device comes out of reset.
production data WM8523 w pd, rev 4.2, august 2013 31 power up and down control in hardware mode in hardware mode the mclk, bclk and mute pins are monitored to control how the device powers up or down, and this is summarised in figure 25 below. off standby enabled bclk enabled mute=1 mute=0 bclk disabled mclk disabled mclk enabled bclk enabled mute=0 mclk enabled bclk enabled mute=1 mclk disabled figure 25 hardware power sequence diagram off to enable to power up the device to enabled, start mclk and bclk and set mute = 1. off to standby to power up the device to standby, start mclk and bclk and set mute = 0. once the device is in standby mode, bclk can be disabled and the device will remain in standby mode. standby to enable to transition from the standby state to the enabled state, set the mute pin to logic 1 and start bclk. enable to standby to power down to a standby state leaving the charge pump running, either set the mute pin to logic 0 or stop bclk. mclk must continue to run in these situations. the device will automatically mute and power down quietly in either case. note: it is recommended that the device is placed in standby mode before samp le rate change if the sample rate changes more than once in 1026 lrclk periods, as detailed in digital audio data sampling rates on page 24. enable to off to power down the device completely, stop mclk at any time. it is recommended that the device is placed into standby mode as described above befor e stopping mclk to allow a quiet shutdown. for the timing of the off state to enabled state tr ansition (power on to audio out timing), and the enabled state to standby state transition (the s hutdown timing), please refer to wtn0302.
WM8523 production data w pd, rev 4.2, august 2013 32 power domains figure 26 power domain diagram power domain name blocks using this domain domain description dac power supplies 3.3v 10% avdd line driver dac dc servo analogue supply 3.3v 10% linevdd charge pump digital ldo digital pad buffers analogue supply internally generated power supplies and references 1.65v 10% vmid dac, ldo ext decoupled resistor string -3.3v 10% cpvoutn line driver charge pump generated voltage table 23 power domains
production data WM8523 w pd, rev 4.2, august 2013 33 register map the complete register map is shown below. the detailed descrip tion can be found in the relevant text of the device description . the WM8523 can be configured using t he control interface. all unused bits should be set to '0' and access to unlisted registers should be avoided. reg name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default r0 (0h) device_id / sw reset chip_id[15:0] 8523h r1 (1h) revision 0 0 0 0 0 0 0 0 0 0 0 0 0 chip_rev[2:0] 0000h r2 (2h) psctrl1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sys_ena[1:0] 0000h r3 (3h) aif_ctrl1 0 0 0 0 0 0 0 dac_ deemp aif_ mstr aif_ lrclk_ inv aif_ bclk_ inv aif_wl[1:0] 0 aif_fmt[1:0] 1812h r4 (4h) aif_ctrl2 0 0 0 0 0 0 0 0 dac_op_mux[1:0] aif_bclkdiv[2:0] aif_sr[2:0] 0000h r5 (5h) dac_ctrl3 0 0 0 0 0 0 0 0 0 0 0 dac_zc dacr_ mute dacl_ mute dac_ vol_ up_ ramp dac_ vol_ down_ ramp 0001h r6 (6h) dac_gainl 0 0 0 0 0 0 dacl_ vu dacl_vol[8:0] 0190h r7 (7h) dac_gainr 0 0 0 0 0 0 dacr_ vu dacr_vol[8:0] 0190h r8 (8h) zero_detect 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 zd_ count 0000h table 24 register map
WM8523 production data w pd, rev 4.2, august 2013 34 register bits by address register address bit label default description refer to r0 (00h) device_id/ sw reset 15:0 chip_id[15:0] 1000_0101_0010_0011 read this register to obtain device id in hex write any value to this register to reset all register values to default. page 18 register 00h device_id / sw reset register address bit label default description refer to r1 (01h) revision 2:0 chip_rev[2:0] 000 device revision number this number is incrementally updated each time the silicon is revised. page 18 register 01h revision register address bit label default description refer to r2 (02h) psctrl1 1:0 sys_ena[1:0] 00 system power control 00 = off 01 = power down 10 = power up to mute 11 = power up to unmute page 25 register 02h psctrl1
production data WM8523 w pd, rev 4.2, august 2013 35 register address bit label default description refer to r3 (03h) aif_ctrl1 8 dac_deemp 0 dac de-emphasis control 0 = no de-emphasis 1 = de-emphasis enabled page 29 7 aif_mstr 0 master/slave select 0 = slave mode 1 = master mode page 22 6 aif_lrclk_ inv 0 lrclk inversion control 0 = normal polarity 1 = inverted polarity when aif_fmt[2:0]=011 (dsp mode): 0 = mode a (2nd clock) 1 = mode b (1st clock) page 22 5 aif_bclk_inv 0 bclk inversion control slave mode: 0 = use rising edge 1 = use falling edge master mode: 0 = bclk normal 1 = bclk inverted page 22 4:3 aif_wl[1:0] 10 audio data word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits page 22 2 reserved 0 reserved 2:0 aif_fmt[1:0] 10 audio data interface format 00 = right justified 01 = left justified 10 = i 2 s format 11 = dsp mode page 22 register 03h aif_ctrl1
WM8523 production data w pd, rev 4.2, august 2013 36 register address bit label default description refer to r4 (04h) aif_ctrl2 7:6 dac_op_ mux[1:0] 00 digital monomix control 00 = stereo (normal operation) 01 = mono (left data to dacr) 10 = mono (right data to dacl) 11 = digital monomix, (l+r)/2 page 29 5:3 aif_ bclkdiv[2:0] 000 bclk divider control (master mode) 000 = mclk/4 001 = mclk/8 010 = 32fs 011 = 64fs 100 = 128fs 101 - 111 reserved page 22 2:0 aif_sr[2:0] 000 mclk:lrclk ratio 000 = auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs page 22 register 04h aif_ctrl2 register address bit label default description refer to r5 (05h) dac_ctrl3 4 dac_zc 0 zero cross enable 0 = do not use zero cross 1 = use zero cross page 26 3 dacr_mute 0 right dac mute 0 = normal operation 1 = mute page 29 2 dacl_mute 0 left dac mute 0 = normal operation 1 = mute page 29 1 dac_vol_ up_ramp 0 dac digital volume increase control 0 = apply volume increases instantly (step) 1 = ramp volume increases page 27 0 dac_vol_ down_ramp 1 dac digital volume decrease control 0 = apply volume decreases instantly (step) 1 = ramp volume decreases page 27 register 05h dac_ctrl3
production data WM8523 w pd, rev 4.2, august 2013 37 register address bit label default description refer to r6 (06h) dac_gainl 9 dacl_vu 0 left dac digital volume update 0 = latch left dac volume setting into register map but do not update volume 1 = latch left dac volume setting into register map and update left and right channels simultaneously page 26 8:0 dacl_vol[8:0] 1_1001_0000 left dac digital volume control 0 0000 0000 = -100db 0 0000 0001 = -99.75db 0 0000 0010 = -99.5db ?0.25db steps 1 1001 0000 = 0db ?0.25db steps 1 1011 1110 = +11.75db 1 11xx xxxx = +12db page 26 register 06h dac_gainl register address bit label default description refer to r7 (07h) dac_gainr 9 dacr_vu 0 right dac digital volume update 0 = latch right dac volume setting into register map but do not update volume 1 = latch right dac volume setting into register map and update left and right channels simultaneously page 26 8:0 dacr_vol[8:0] 1_1001_0000 right dac digital volume control 0 0000 0000 = -100db 0 0000 0001 = -99.75db 0 0000 0010 = -99.5db ?0.25db steps 1 1001 0000 = 0db ?0.25db steps 1 1011 1110 = +11.75db 1 11xx xxxx = +12db page 26 register 07h dac_gainr register address bit label default description refer to r8 (08h) zero_ detect 0 zd_count[1:0] 0 zero detect count control 0 = 1024 1 = 2048 page 29 register 08h zero_detect
WM8523 production data w pd, rev 4.2, august 2013 38 digital filter characteristics parameter test conditions min typ max unit dac filter ? 256fs to 1152fs passband ? 0.1db 0.454fs passband ripple 0.1 db stopband 0.546fs stopband attenuation f > 0.546fs -50 db group delay 14.5 fs dac filter ? 128fs and 192fs passband ? 0.1db 0.247fs passband ripple 0.1 db stopband 0.753fs stopband attenuation f > 0.753fs -50 db group delay 6.5 fs terminology 1. stop band attenuation (db) ? the degree to which the frequency spectrum is attenuated (outside audio band) 2. pass-band ripple ? any variation of t he frequency response in the pass-band region
production data WM8523 w pd, rev 4.2, august 2013 39 dac filter responses -120 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 frequency (fs) response (db) -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (fs) response (db) figure 27 dac digital filter frequency response ? 256fs to 1152fs clock modes figure 28 dac digital filter ripple ? 256fs to 1152fs clock modes -100 -80 -60 -40 -20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (fs) response (db) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0 0.050.10.150.20.250.30.350.40.450.5 frequency (fs) response (db) figure 29 dac digital filter frequency response ? 128fs and 192fs clock modes figure 30 dac digital filter ripple ? 128fs to 192fs clock modes
WM8523 production data w pd, rev 4.2, august 2013 40 digital de-emphasis characteristics -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) figure 31 de-emphasis frequency response (32khz) figure 32 de-emphasis error (32khz) figure 33 de-emphasis frequency response (44.1khz) figure 34 de-emphasis error (44.1khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 5 10 15 20 response (db) frequency (khz) figure 35 de-emphasis frequency response (48khz) figure 36 de-emphasis error (48khz)
production data WM8523 w pd, rev 4.2, august 2013 41 applications information recommended external components mclk bclk lrclk dacdat dacdat lrclk bclk mclk sdout/deemph sdout/deemph sda/aifmode0 sda/aifmode0 sclk/aifmode1 sclk/aifmode1 cs/mute cs/mute cifmode cifmode zflag zflag 11 10 9 8 12 13 14 15 16 7 avdd linevdd cpvoutn linevoutr linevoutl cpca cpcb linevdd 19 6 2 linegnd agnd vmid 4 17 18 c1 c2 c3 c4 c5 avdd 5 3 1 20 1uf 4.7uf 4.7uf 2.2uf 1uf WM8523 figure 37 recommended external components notes: 1. wolfson recommend using a single, common ground plane. where this is not possible, care should be taken to optimise split ground configuration for audio performance. 2. charge pump fly-back capacitor c5 should be placed as close to WM8523 as possible, followed by charge pump decoupling capacitor c1, then linevdd and vmid decoup ling capacitors. see recommended pcb layout on p42. 3. capacitor types should be chosen carefully. capac itors with very low esr are recommended for optimum performance.
WM8523 production data w pd, rev 4.2, august 2013 42 recommended pcb layout avdd linegnd cpcb cpca cpvoutn linevdd agnd vmid figure 38 recommended pcb layout notes: 1. c5 should be placed as close to wm 8523 as possible, with minimal track l engths to reduce inductance and maximise performance of the charge pump. vias should be avoided in the tracking to c5. 2. c1 is then next most important and should also be placed as close as possible to the wm 8523. again, minimise track lengths and avoid vias to r educe parasitic inductance. 3. c2 and c4 are then next most important, and lastly c3. 4. the WM8523 evaluation board, details available at www.wolfsonmicro.com , shows an example of good component placement and layout to maximise performance with a minimal bom.
production data WM8523 w pd, rev 4.2, august 2013 43 recommended analogue low pass filter figure 39 recommended analogue low pass filter (one channel shown) an external single-pole rc filter is recommended if the device is driving a wideband amplifier. other filter architectures may provide equally good results. the filter shown in figure 39 has a -3db cut-off at 105.26khz and a droop of 0.15db at 20khz. the typical output from the WM8523 is 2.1vrms ? when a 10k ? load is placed at the output of this recommended filter the amplitude across this load is 1.99vrms. relevant application notes the following application notes, available from www.wolfsonmicro.com , may provide additional guidance for use of the WM8523. device performance: wan0129 ? decoupling and layout methodology for wolfson dacs, adcs and codecs wan0144 ? using wolfson audio dacs and codecs with noisy supplies wtn0302 - wm8524 recommended power sequence and timing (for hardware mode) general: wan0108 ? moisture sensitivity cla ssification and plastic ic packaging wan0109 ? esd damage in integrated circuits: causes and prevention wan0158 ? lead-free solder profiles for lead-free components wan0161 ? electronic end-product design for esd
WM8523 production data w pd, rev 4.2, august 2013 44 package dimensions ? c l gauge plane 0.25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.25mm. d. meets jedec.95 mo-153, variation = ac. refer to this specification for further details. dm008.d dt: 20 pin tssop (6.5 x 4.4 x 1.0 mm) symbols dimensions (mm) min nom max a ----- ----- 1.20 a 1 0.05 ----- 0.15 a 2 0.80 1.00 1.05 b 0.19 ----- 0.30 c 0.09 ----- 0.20 d 6.40 6.50 6.60 e 0.65 bsc e 6.4 bsc e 1 4.30 4.40 4.50 l 0.45 0.60 0.75 ? 0 o ----- 8 o ref: jedec.95, mo-153 a a2 a1 seating plane 11 20 e1 e e b 10 1 d -c- 0.1 c
production data WM8523 w pd, rev 4.2, august 2013 45 important notice wolfson microelectronics plc (?wol fson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at the date of shipment. wolfson reserves the right to make changes to its products and s pecifications or to discont inue any product or service without notice. customers should therefore obtain the latest version of relevant informati on from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless requi red by law or regulation. in order to minimise risks associated with customer app lications, the customer must use adequate design and operating safeguards to minimise inherent or proc edural hazards. wolfson is not liable fo r applications assistance or customer product design. the customer is solely responsible for its se lection and use of wolfson products . wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to re sult in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or pr ocess in which its products or services might be or are used. any prov ision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is per missible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other not ices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such in formation or for any reliance placed thereon. any representations made, warranties giv en, and/or liabilities accepted by any pers on which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: apps@wolfsonmicro.com
WM8523 production data w pd, rev 4.2, august 2013 46 revision history date rev originator changes page 23/08/10 4.1 bt added minimum a-weighted snr limit of 100db 9 bt changed group delay of 256/128fs filters from 10fs to 14.5fs and 6.5fs 40 05/07/13 4.2 jmacd qfn part removed from datasheet. various

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